Ruijie Jerry Gao | University of Glasgow & UESTC

About Me

I am currently final-year undergrad pursuing a B.Eng. in a dual-degree program from the University of Glasgow and UESTC. I had the opportunity to gain valuable experience under the mentorship of Dr. Yu Zeng from Princeton University, during a research collaboration that spanned from the fall of 2022 to the summer of 2023. From August 2023 to December 2023, I joined the EIC Lab at GaTech, where I worked under the supervision of Dr. Yang (Katie) Zhao. Most recently, from May to September 2024, I was enrolled in the Synthesis Lab, KAUST where I conducted research under the mentorship of Prof. Jian Weng.

I am actively seeking PhD opportunities starting from 2025 Fall in Computer Architecture and Electronic Design Automation (EDA).

Research Interests

Programming Abstraction for Accelerators
Formal Verification & Logic Synthesis
Agile Accelerator Design
Hardware/Software Co-design

News

[June 2024] I just held the final review session for UESTC1008: Microelectronic Systems. The slides are available here. Good luck with your exam!
[Mar. 2024] Our paper EDGE-LLM is accepted to DAC 2024.

Publications

DAC

EDGE-LLM: Enabling Efficient Large Language Model Adaptation on Edge Devices via Unified Compression and Adaptive Layer Voting

Zhongzhi Yu, Zheng Wang, Yuhan Li, Haoran You, Ruijie Gao, Xiaoya Zhou, Sreenidhi Reddy Bommu, Yang (Katie) Zhao, and Yingyan (Celine) Lin

Design Automation Conference (DAC), 2024.

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Teaching

Lead Teaching Assistant, Embedded Processors, 2024 Spring
Teaching Assistant, Microelectronic Systems, 2024 Spring
Teaching Assistant, Introductory Programming, 2022 Fall, 2023 Fall, 2024 Fall