æSIP: μArch-aware ASIP-ISA Co-Design via Program Synthesis, Equality Saturation, and External Don't Cares

An increasing number of applications, including implantables, IoT devices, and printed electronics, impose stringent power and area constraints. With the end of Dennard scaling, Application Specific Instruction Processors (ASIPs) have emerged as a promising solution, reducing power consumption and silicon area by sacrificing generality compared to general-purpose processors. However, existing approaches predominantly optimize hardware through software profiling, potentially overlooking optimization opportunities through software rewriting. We propose æSIP, a hardware-software co-optimization framework for efficient ASIP design. Our framework leverages e-graph data structures to explore semantically equivalent software implementations through rewriting rules derived from program synthesis. We employ a divide-and-conquer approach that performs local saturation at basic-block granularity followed by Integer Linear Programming (ILP)-based global extraction at whole-program scope, enabling scalability to real-world applications. We develop a don't care-based hardware optimizer that automatically generates ASIP designs for each equivalent program variant, enabling agile design space exploration. We further incorporate a constraint-based sharing algorithm that clusters applications with similar characteristics and limits the number of ASIP variants, thereby enabling efficient reuse across workloads and balancing area/power efficiency with NRE cost. To our knowledge, this represents the first systematic hardware–software co-design framework for agile multi-objective ASIP development. Experimental evaluation on widely used embedded benchmark suites, MiBench and Embench, demonstrates geometric mean area reduction of 17.0% and power savings of 12.3% compared to state-of-the-art ASIP generators. When energy is the optimization objective, æSIP achieves geometric mean energy reductions of 4.1% (CMOS 130 nm) and 6.3% (Inkjet Printed Electronics process). Furthermore, æSIP enables generalization across diverse workloads while preserving specialization. Our trade-off analysis shows that with only five shared ASIPs, æSIP achieves a 17.3% area reduction with 11.9% latency overhead, compared to 22.4% area reduction and 15.1% latency overhead under full per-application specialization.